A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF
This paper presents a high noise efficiency readout circuit for multi-channel bio-signal acquisition. The prototype is implemented in a 65 nm CMOS LP process, which achieves a power consumption of 2.06 \muW/channel, a noise efficiency factor (NEF) of1.48, a common-mode rejection ratio (CMRR) of 105...
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Published in | ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC) pp. 5 - 8 |
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Main Authors | , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
11.09.2023
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Subjects | |
Online Access | Get full text |
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Summary: | This paper presents a high noise efficiency readout circuit for multi-channel bio-signal acquisition. The prototype is implemented in a 65 nm CMOS LP process, which achieves a power consumption of 2.06 \muW/channel, a noise efficiency factor (NEF) of1.48, a common-mode rejection ratio (CMRR) of 105 dB at 50 Hz, and a crosstalk of -65dB by employing these new techniques, including 1) the use of single-ended amplifiers as the unit of low noise amplifier (LNA) for lower NEF, 2) single-end chopping techniques for single-ended amplifiers for suppressing low-frequency noise and offset, 3) digital-assisted DC servo loop (DDSL) for fast settling. |
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ISSN: | 2643-1319 |
DOI: | 10.1109/ESSCIRC59616.2023.10268787 |