Proteus : HLS-based NoC Generator and Simulator

• Published in: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 1 - 6
• Main Authors: Bambhaniya, Abhimanyu Rajeshkumar, Chen, Yangyu, Anshuman, Banerjee, Rohan, Krishna, Tushar
• Format: Conference Proceeding
• Language: English
• Published: EDAA 01.04.2023
• Subjects: C++ languages; Chisel; FPGA; Generators; Hardware; NoC Generator; NoC Simulator; Routing; Software; Software algorithms; Topology; Vitis HLS
• ISSN: 1558-1101
• DOI: 10.23919/DATE56975.2023.10137173

Networks-on-chip (NoCs) form the backbone fabric for connecting multi-core SoCs containing several processor cores and memories. Design-space exploration (DSE) of NoCs is a crucial part of the SoC design process to ensure that it does not become a bottleneck. DSE today is often hindered by the inherent trade-off between software simulation vs hardware emulation/e- valuation. Software simulators are easily extendable and allow for the evaluation of new ideas but are not able to capture the hardware complexity. Meanwhile, RTL development is known to be time-consuming. This has forced DSE to use simulators followed by RTL development, evaluation and feedback, which slows down the overall design process. In an effort to tackle this problem, we present Proteus, a configurable and modular NoC simulator and RTL generator. Proteus is the first of its kind framework to use HLS compiler to develop NoCs from a C++ description of the N oC circuit. These generated N oCs can be simulated in software and tested on FPGAs. This allows users to do rapid DSE by providing the opportunity to tweak and test NoC architectures in real-time. We also compare Proteus-generated RTL with Chisel- generated and hand-written RTL in terms of area, timing and productivity. The ability to synthesize the NoC design on FPGAs can benefit large designs as the custom hardware results in faster run-time than cycle-accurate software simulators. Proteus is modeled similar to existing state-of-the-art simulators and offers users modifiable parameters to generate custom topologies, routing algorithms, and router microarchitectures.