An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs

Moving toward software-defined networking and function virtualization, flexibility and reconfigurability of the network have become more and more critical. Packet parsing, the first processing stage of programmable switches, requires high performance and reconfigurability to allow implementing low-l...

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Bibliographic Details
Published in2023 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
Main Authors Mashreghi-Moghadam, Parisa, Ould-Bachir, Tarek, Savaria, Yvon
Format Conference Proceeding
LanguageEnglish
Published IEEE 21.05.2023
Subjects
Codes
FPGA
Hardware
Memory architecture
over-lay
P4 language
packet parser
Pipelines
prototyping
SDN
Table lookup
Throughput
Virtualization
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Summary:Moving toward software-defined networking and function virtualization, flexibility and reconfigurability of the network have become more and more critical. Packet parsing, the first processing stage of programmable switches, requires high performance and reconfigurability to allow implementing low-latency and highly flexible data networks. This paper proposes an overlay architecture for an FPGA-based P4-programmable streaming packet parser. The purpose of this architecture is to allow supporting different functionality with a fixed hardware design by changing a program stored in an embedded memory. This program is derived from the parser section of a P4 code, describing a parsing graph. This approach eliminates a pipeline of parsing blocks in favor of a single parsing block, thereby reducing the design's complexity. Our architecture offers an 11 Gb/s data rate on a Xilinx Virtex-7 XC7VX690 FPGA, while its implementation requires 312 LUTs and 1135 FFs.
ISSN:2158-1525
DOI:10.1109/ISCAS46773.2023.10182176