MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain-Computer Interfaces

• Published in: 2023 IEEE 41st International Conference on Computer Design (ICCD) pp. 70 - 77
• Main Authors: Eichler, Guy, Seyoum, Biruk, Chiu, Kuan-Lin, Carloni, Luca P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 06.11.2023
• Subjects: BCI; Brain-computer interfaces; DPR; Energy efficiency; FPGA; Generators; HLS; P2P; RISC-V; SoC; Software; System-on-chip; Throughput; Usability
• ISSN: 2576-6996
• DOI: 10.1109/ICCD58817.2023.00021

True random number generation on resource-constrained devices is challenging due to inherent hardware limitations; these limitations affect the ability to find a reliable source of randomness with high throughput and sufficient entropy. As recent developments in the field of Brain-Computer Interfaces (BCI) suggest a wide range of future applications that require random numbers, we investigate the usability of electrocorticography-based neural data as seeds for random number generation. We develop algorithms that generate random bits from brain data and evaluate the quality of randomness by using the NIST SP 800-22 test suite. We implement the algorithms as hardware random bit generators (RBGs). Then, we integrate these implementations as hardware accelerators in MindCrypt, a heterogeneous System-on-Chip (SoC) that is equipped with a host processor to run BCI applications. In MindCrypt, applications use our RBG accelerators as random number generators (RNGs) and prime number generators. FPGA prototypes of MindCrypt running software applications on a RISC-V processor that invoke our accelerators show improvements of 376x in throughput and 4885x in energy efficiency compared to using state-of-the-art Linux-based RNGs. By transferring random bits with point-to-point (P2P) communication between the RBG accelerators and cryptographic accelerators, we gain 6.1x in performance and 12.4x in energy efficiency compared to direct memory access (DMA). Finally, we explore the efficacy of a partially reconfigurable FPGA implementation of MindCrypt that dynamically optimizes the throughput of random number generation in a resource-constrained BCI SoC.