Algorithm-Aware Digital Design for Analog-on-Top Chips: An ASK Demodulator Comparative Study

• Published in: 2023 IEEE SENSORS pp. 1 - 4
• Main Authors: Tecce, Felice, Abate, Matteo, Del Prete, Francesco, Cirillo, Giovanni Amedeo, Parrella, Claudio, Castellano, Marco
• Format: Conference Proceeding
• Language: English
• Published: IEEE 29.10.2023
• Subjects: Amplitude shift keying; Catapult; Hardware; Hardware Description Language; High-Language Hardware; High-Level Synthesis; IP digital design; Sensor phenomena and characterization; Signal processing algorithms; Software; Software algorithms; SpinalHDL; SystemVerilog; Transducers
• ISSN: 2168-9229
• DOI: 10.1109/SENSORS56945.2023.10325037

Design of application-specific Digital Signal Processing elements is related to the implementation of an algorithm, initially implemented in software. The time-to-design can be extremely long, especially when design space exploration must be done and hardware description must be written from scratch. Different tools are nowadays available to generate a Register Transfer Level (RTL) circuit and corresponding testbenches from software, even with routines for design space exploration. These tools are based on High-Level Synthesis (HLS) and High-Language Hardware description (HLH) paradigms. This work compares the RTLs for an integrated digital Amplitude Shift Keying demodulator, employable either for the recognition of messages detected by transducers or in sensors networks. SystemVerilog, Catapult HLS from Siemens EDA and SpinalHDL were considered for canonical hardware description, HLS and HLH respectively. Synthesis results with three STMicroelectronics technologies prove that the RTLs automatically generated by SpinalHDL and Catapult provide area results comparable with those obtained with from-scratch design in SystemVerilog and can also achieve better performance in terms of dynamic power.