Transition from Synchronous to Asynchronous Systems with Minimal Logic Changes

This paper examines the transition from syn-chronous to asynchronous microprocessor systems as a response to the physical and technological limits reached in terms of transistor size reduction and internal circuitry. The implementation of the delay-insensitive, dual-rail, 4-phase methodology in a mi...

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Bibliographic Details
Published in2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS) pp. 1 - 5
Main Authors Carlos Garcia Lopez, Juan, Ortega-Cisneros, S., Isaac Baungarten-Leon, Emilio, Vazquez-Robles, M., Rivera Dominguez, Jorge
Format Conference Proceeding
LanguageEnglish
Published IEEE 27.02.2024
Subjects
Asynchronous circuits
Asynchronous Control Block (ACB)
Clock signal
Control Unit (CU)
Double-rail 4-phase protocol
Energy efficiency
Heating systems
Layout
Microprocessor
Microprocessors
Muller C gates
Power consumption
Power demand
Simulation
Stability analysis
Technological innovation
von Neumann
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Summary:This paper examines the transition from syn-chronous to asynchronous microprocessor systems as a response to the physical and technological limits reached in terms of transistor size reduction and internal circuitry. The implementation of the delay-insensitive, dual-rail, 4-phase methodology in a microprocessor based on the von Neumann architecture is studied, using a technique that reduces to a minimum the changes required in the register transfer level (RTL) design, while pre-serving the designs used in synchronous logic. Simulation results show that asynchronous systems outperform their synchronous counterparts by 90.9% in terms of power consumption. This approach represents a promising perspective for the evolution of digital technology, opening up new opportunities and challenges for the future.
ISSN:2473-4667
DOI:10.1109/LASCAS60203.2024.10506182