Asymmetric Aging Avoidance EDA Tool

The latest process technologies have become highly susceptible to asymmetric aging, whereby the timing of logical elements degrades at unequal rates over the element lifetime, causing severe reliability concerns. Although several tools are available to handle asymmetric aging, such tools mainly rely...

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Bibliographic Details
Published in2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) pp. 1 - 6
Main Authors Gabbay, Freddy, Mendelson, Avi, Salameh, Basel, Ganaiem, Majd
Format Conference Proceeding
LanguageEnglish
Published IEEE 23.08.2021
Subjects
Aging
Asymmetric Aging
Asymmetric Aging aware EDA
Bias Temperature Instability
Integrated circuits
Logic gates
Reliability
Reliability engineering
Silicon
Timing
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Summary:The latest process technologies have become highly susceptible to asymmetric aging, whereby the timing of logical elements degrades at unequal rates over the element lifetime, causing severe reliability concerns. Although several tools are available to handle asymmetric aging, such tools mainly rely on circuit or physical design approaches and offer a limited capability to handle large-scale ICs. In this paper, we introduce a flow and a tool to minimize the asymmetric aging effect in data path design structures. The proposed tool can be straightforwardly integrated as part of standard design flows of large-scale ICs. In addition, the tool can automatically analyze various designs at RTL or gate-level and identify logical elements which are suspectable to asymmetric aging. As part of the design flow, the tool automatically embeds a special logical circuitry in the design to eliminate asymmetric aging. Our experimental analysis shows that the proposed design flow can minimize the asymmetric aging effect and eliminate reliability concerns while introducing minor power and silicon area overhead.
DOI:10.1109/SBCCI53441.2021.9529984