Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis

Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. Conventionally, accurate diagnosis requires a sufficient amount of failing data, indicating a high test cost. Prior work that...

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Bibliographic Details
Published in2021 IEEE 39th VLSI Test Symposium (VTS) pp. 1 - 7
Main Authors Fang, Chenlei, Huang, Qicheng, Blanton, R. D. Shawn
Format Conference Proceeding
LanguageEnglish
Published IEEE 25.04.2021
Subjects
Clustering algorithms
Heuristic algorithms
Memory management
Very large scale integration
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Summary:Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. Conventionally, accurate diagnosis requires a sufficient amount of failing data, indicating a high test cost. Prior work that attempt to solve this problem either use a fixed pattern order, ignoring the characteristics of each chip, or require significant memory which leads to unacceptable increases in test cost. In this work, a new algorithm is described for dynamically selecting the test pattern order that leads to significant reduction in memory cost. Experiments using two industrial chips demonstrate the efficacy of the approach. Compared to prior work, the algorithm described in this work uses as little as 1/500 of tester space to store failing data.
ISSN:2375-1053
DOI:10.1109/VTS50974.2021.9441003