Research on High-speed SerDes Interface Testing Technology

At present, the demand for high-speed data transmission is getting higher and higher. Due to technological progress, the clock frequency is getting higher and higher. Compared with the parallel interface, the serial interface has fewer wires and less interference between wires [1]. The transmission...

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Bibliographic Details
Published in2021 22nd International Conference on Electronic Packaging Technology (ICEPT) pp. 1 - 5
Main Authors Xie, Weikun, Cao, Guangqiang, Ji, Weiwei
Format Conference Proceeding
LanguageEnglish
Published IEEE 14.09.2021
Subjects
automated testing
bit error rate
Built-in self-test
Data communication
eye diagram
Hardware
Instruments
Interference
Ports (computers)
SerDes
V93000
Wires
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Summary:At present, the demand for high-speed data transmission is getting higher and higher. Due to technological progress, the clock frequency is getting higher and higher. Compared with the parallel interface, the serial interface has fewer wires and less interference between wires [1]. The transmission rate is improved by continuously increasing the clock frequency. Effective verification and testing of the highspeed serial port SerDes chip is worth studying. This article introduces a method to test the high-speed SerDes serial interface based on the V93000 test system. A FPGA product with a model of XCKU040 is used as the chip to be tested, and the sending/receiving function test of the SerDes interface chip with a transmission rate of 16Gbps is carried out. A hardware test PCB platform with FPGA as the core was built, and the chip was tested in various working modes, including inner loop mode, outer loop mode, and built-in self-test mode. The hardware test PCB platform based on FPGA is established, and the functions of TX and Rx are tested.
DOI:10.1109/ICEPT52650.2021.9567964