1/f-Noise and Offset Cancellation for Rail-to-Rail Single-Slope ADCs in MEA Applications

• Published in: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) pp. 1 - 5
• Main Authors: Straczek, Lukas, Veit, Dominik J., Oehm, Jurgen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2019
• Subjects: 1/f-noise cancelling; chopper techniques; CMOS; MEA; microelectrode array; mixed-signal; numerical in-time correction; offset cancelling; PVT; rail-to-rail; single-slope ADC
• DOI: 10.1109/NORCHIP.2019.8906972

Process, voltage, temperature variations (PVT), mismatch, and noise typically influence the conversion accuracy of an analog-to-digital converter (ADC). This paper presents a novel rail-to-rail single-slope ADC concept that combines chopper comparators with some special numerical methods capable of deterministically eliminating the effects of 1/f-noise and local transistor mismatch without increasing the conversion time. The proposed numerical arithmetic can be performed with minimal hardware effort. In order to achieve maximum conversion speed, this paper also presents a numerical extension of the proposed basic concept. Therefore a second counter for an alternating evaluation of the conversion is used. The single-slope ADC design concept presented in this paper is particularly suitable for use in microelectrode array structures (MEAs). Therefore, the presented structures are modularized in such a way that a minimal part of the ADC circuitry is always within an active array pixel and the rest is outside the pixel arrangement as a common circuit part of a row or column. For this work the data of a 180 nm CMOS technology was base and the functionality was verified by nominal and statistical simulations.