Risk-Aware Cost-Effective Design Methodology for Integrated Circuit Locking

We introduce a systematic framework for logic locking of integrated circuits based on the analysis of the sources of information leakage from both the circuit and the locking scheme and their formalization into a notion of risk that can guide the design against existing and possible future attacks....

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Bibliographic Details
Published inProceedings - Design, Automation, and Test in Europe Conference and Exhibition pp. 1182 - 1185
Main Authors Hu, Yinghua, Yang, Kaixin, Chowdhury, Subhajit Dutta, Nuzzo, Pierluigi
Format Conference Proceeding
LanguageEnglish
Published EDAA 01.02.2021
Subjects
Cost function
Design methodology
Hardware
Hardware security
Integrated circuits
logic locking
risk modeling
Security
Systematics
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Summary:We introduce a systematic framework for logic locking of integrated circuits based on the analysis of the sources of information leakage from both the circuit and the locking scheme and their formalization into a notion of risk that can guide the design against existing and possible future attacks. We further propose a two-level optimization-based methodology to generate locking strategies minimizing a cost function and balancing security, risk, and implementation overhead, out of a collection of locking primitives. Optimization results on a set of case studies show the potential of layering multiple locking primitives to provide high security at significantly lower risk.
ISSN:1558-1101
DOI:10.23919/DATE51398.2021.9473956