Memristor-Specific Failures: New Verification Methods and Emerging Test Problems

• Published in: 2022 IEEE 40th VLSI Test Symposium (VTS) pp. 1 - 7
• Main Authors: Biswas, Baishakhi Rani, Gupta, Sandeep
• Format: Conference Proceeding
• Language: English
• Published: IEEE 25.04.2022
• Subjects: Cascading; Logic circuits; Logic failure; Memristor Ratioed Logic; Memristors; Power system protection; Switches; Systematics; Test pattern; Verification; Very large scale integration; Voltage
• ISSN: 2375-1053
• DOI: 10.1109/VTS52500.2021.9794274

We study two types of memristor-specific logic failures in Memristor Ratioed Logic (MRL), an extensively studied Memristor-CMOS hybrid logic design style. Cascading failures have been previously observed as causing significant voltage degradation, and hence logic values errors, in certain MRL logic circuits. Here, we present the first systematic study of this type of logical error and identify its key properties as a function of circuit structure and patterns applied. We then propose a method to generate patterns that cause the worst-case output voltage for a given MRL circuit and hence facilitate pre-fabrication verification. We then present the first study of another type of logic failure for voltage controlled memristor devices, namely a race when memristors in series, and with the same polarity, switch states from Ron to Roff. We show that such a race can cause non-deterministic behavior depending on circuit structure, values of memristor parameters, and the initial states of memristors when a pattern is applied. We then generate patterns and initial states that excite such race and hence potentially cause logic errors to enable verification.