UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS

A new and improved Unified Clock and Power (UniCaP) architecture relies on dual-path feedback to further reduce supply-voltage (V dd ) margins in an ARM Cortex M0 processor while minimizing both peak cycle loss (Δϕ max ) and cycle-loss recovery time (T recovery ) associated with adaptive clocking. M...

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Bibliographic Details
Published in2020 IEEE Symposium on VLSI Circuits pp. 1 - 2
Main Authors Sun, Xun, Boora, Akshat, Pamula, Rajesh, Huang, Chi-Hsiang, Pena-Colaiocco, Diego, Sathe, Visvesh S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2020
Subjects
Clocks
Delays
Phase measurement
Semiconductor device measurement
Sensitivity
Sun
Transient analysis
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Summary:A new and improved Unified Clock and Power (UniCaP) architecture relies on dual-path feedback to further reduce supply-voltage (V dd ) margins in an ARM Cortex M0 processor while minimizing both peak cycle loss (Δϕ max ) and cycle-loss recovery time (T recovery ) associated with adaptive clocking. Measurements on a 65nm test chip demonstrate 91-99% V dd margin reduction and 38X T recovery improvement over [3]. We also report measurements that quantify the impact of clock distribution delay (τ dist ) and V dd sensitivity on V dd margin reduction.
ISSN:2158-5636
DOI:10.1109/VLSICircuits18222.2020.9162982