Tileable Monolithic ReRAM Memory Design

Non-volatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint sub-arrays that leave the bulk of transistors underneath the sub-arrays...

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Bibliographic Details
Published in2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) pp. 1 - 3
Main Authors Jagasivamani, Meenatchi, Walden, Candace, Singh, Devesh, Kang, Luyi, Asnaashari, Mehdi, Dubois, Sylvain, Jacob, Bruce, Yeung, Donald
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2020
Subjects
Central Processing Unit
Crosspoint architectures
Integrated circuit interconnections
Memory management
Metals
Random access memory
ReRAM and on-die main memory systems
Three-dimensional displays
Transistors
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Summary:Non-volatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint sub-arrays that leave the bulk of transistors underneath the sub-arrays vacant. This permits placing the memory system over other logic. We propose a tileable, centralized ReRAM design over a large last level cache. This design takes advantage of ReRAMs unique characteristics while still providing flexibility to designers.
ISSN:2473-4683
DOI:10.1109/COOLCHIPS49199.2020.9097632