Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor
In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert...
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Published in | 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 1077 - 1082 |
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Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
EDAA
14.03.2022
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Subjects | |
Online Access | Get full text |
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Summary: | In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06\times 10^{6} DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively. |
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ISSN: | 1558-1101 |
DOI: | 10.23919/DATE54114.2022.9774584 |