Improving Test Chip Design Efficiency via Machine Learning

• Published in: 2019 IEEE International Test Conference (ITC) pp. 1 - 10
• Main Authors: Liu, Zeye, Huang, Qicheng, Fang, Chenlei, Blanton, R. D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2019
• ISSN: 2378-2250
• DOI: 10.1109/ITC44170.2019.9000131

Competitive position in the semiconductor field depends on yield which is becoming more challenging to achieve high levels due to the increasing complexity associated with the design and fabrication of leading-edge integrated circuits (ICs). Consequently, test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process before and during product ramp. However, designing a high quality full-flow logic test chip can be time-consuming due to the huge design space. This work describes a design methodology that deploys a random forest classification technique to predict synthesis outcomes for test chip design exploration. Experiments on creating five full-flow logic test chips, which mimic five different designs, demonstrate the efficacy of the proposed methodology. To be specific, those design experiments demonstrate that the machine learning aided flow speeds up design by 11× with negligible performance degradation.