A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application

• Published in: Proceedings of the Custom Integrated Circuits Conference pp. 1 - 2
• Main Authors: Rasul, Rezwan A, Chen, Mike Shuo-Wei
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2021
• Subjects: Limiting; Linearity; Machine learning algorithms; Memory management; Ports (computers); Power demand; Random access memory
• ISSN: 2152-3630
• DOI: 10.1109/CICC51472.2021.9431485

In-memory computing (IMC) has emerged as an attractive alternative to conventional digital implementation of machine learning algorithm, since it can achieve high energy efficiency by limiting the data movement between memory and processing unit. In prior IMC works, multi-bit input is encoded into either pulse count [2] or pulse width [4] or an analog voltage [1], [3], [5] using a DAC which drives the read bit-line (RBL) or read word-line (RWL) port of the bit cell. Such current-domain computation suffers from static power consumed by the DAC and is limited by the linearity of the current sources necessitating calibration [2]. In comparison, charge-domain computation relaxes the linearity, and static power consumption issue; however, prior work has only explored limited parameter precision, i.e. BNN, and is subject to signal attenuation due to charge loss over parasitic elements [6]. Moreover, those prior arts [1 - 6] lack support of either negative input or negative/zero weights, preventing from implementing a wider range of networks in the IMC hardware.