A Sub-1 V, 120 nW, PVT-Variation Tolerant, Tunable, and Scalable Voltage Reference With 60-dB PSNA

• Published in: IEEE transactions on nanotechnology Vol. 16; no. 3; pp. 406 - 410
• Main Authors: Chatterjee, Baibhab, Modak, Nirmoy, Amaravati, Anvesha, Mistry, Deep, Das, Devarshi Mrinal, Baghini, Maryam Shojaei
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; Chip formation; CMOS; CMOS technology; Coefficient of variation; CTAT; Electric potential; Electronics; Generators; Integrated circuits; low-power; PTAT; PVT; scalable; Semiconductor device measurement; sub-threshold; Switching; System on chip; Temperature; Temperature measurement; Threshold voltage; Transistors; tunable; Voltage measurement; voltage reference; Zero temperature coefficient
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2017.2656161

This paper presents a novel low-power process, voltage and temperature (PVT)-variation tolerant voltage reference generator that can be easily redesigned across various CMOS technologies. The proposed circuit architecture can be used in standalone analog integrated circuits that may not require nano-scale technologies as well as system-on-a-chip applications that need analog circuits in a much lower technology node due to their dominant digital counterparts. The reference generator implements weighted averaging of a PTAT (proportional to absolute temperature) and a CTAT (complementary to absolute temperature) voltage at zero temperature coefficient (ZTC) point. PVT-variation tolerant behavior is achieved by using an on-chip shift register based switching circuit that adjusts the bias current of a key transistor in the circuit. The proposed reference generator is fabricated in 180 nm mixed-mode CMOS technology and also designed in 65 and 28 nm technologies using foundry provided models. For a temperature range from 0 to 75 °C at 1.8 V supply, the measured tuned output voltage varies by only ±0.33% across 17 chips, which is significantly lower than all previously reported works.