DRAM-Less: Hardware Acceleration of Data Processing with New Memory

• Published in: 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA) pp. 287 - 302
• Main Authors: Zhang, Jie, Park, Gyuyoung, Donofrio, David, Shalf, John, Jung, Myoungsoo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2020
• Subjects: Acceleration; accelerator; Buffer storage; data movement; Data processing; FPGA controller; Hardware; Kernel; near-data processing; Phase change random access memory
• ISSN: 2378-203X
• DOI: 10.1109/HPCA47549.2020.00032

General purpose hardware accelerators have become major data processing resources in many computing domains. However, the processing capability of hardware accelerations is often limited by costly software interventions and memory copies to support compulsory data movement between different processors and solid-state drives (SSDs). This in turn also wastes a significant amount of energy in modern accelerated systems. In this work, we propose, DRAM-less, a hardware automation approach that precisely integrates many state-of-the-art phase change memory (PRAM) modules into its data processing network to dramatically reduce unnecessary data copies with a minimum of software modifications. We implement a new memory controller that plugs a real 3x nm multi-partition PRAM to 28nm technology FPGA logic cells and interoperate its design into a real PCIe accelerator emulation platform. The evaluation results reveal that our DRAM-less achieves, on average, 47% better performance than advanced acceleration approaches that use a peer-to-peer DMA.