GSM 900/DCS 1800 fractional-N frequency synthesizer with very fast settling time

This paper presents a programmable phase-locked-loop (PLL)-based fractional-N frequency synthesizer that uses a third-order /spl Delta//spl Sigma/-modulator. The in-band phase noise of -97 dBc/Hz in the integer-mode and -94 dBc/Hz in the fractional-mode is measured at 30 kHz offset. In addition to o...

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Published in2001 IEEE MTT-S International Microwave Sympsoium Digest (Cat. No.01CH37157) Vol. 2; pp. 705 - 708 vol.2
Main Authors Neurauter, B., Marzinger, G., Luftner, T., Weigel, R., Scholz, M., Mutlu, V., Fenk, J.
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 2001
Subjects
Distributed control
Frequency synthesizers
GSM
Noise measurement
Phase locked loops
Phase measurement
Phase noise
Radio frequency
RF signals
Throughput
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Summary:This paper presents a programmable phase-locked-loop (PLL)-based fractional-N frequency synthesizer that uses a third-order /spl Delta//spl Sigma/-modulator. The in-band phase noise of -97 dBc/Hz in the integer-mode and -94 dBc/Hz in the fractional-mode is measured at 30 kHz offset. In addition to offering an ultra-fine frequency resolution of down to 12.4 Hz and very low in-band phase noise this frequency synthesizer offers, with a loop-bandwidth of about 100 kHz, a very fast settling time of less than 95 /spl mu/s when a 75 MHz jump is applied. This feature enables multiple RF applications, including GSM to send a signal and quickly reset to send another signal to meet high data throughput requirements.
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ISBN:0780365380
9780780365384
ISSN:0149-645X
2576-7216
DOI:10.1109/MWSYM.2001.966991