A dual execution pipelined floating-point CMOS processor

• Published in: 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Vol. 39; pp. 358 - 359
• Main Authors: Kowaleski, J.A., Wolrich, G.M., Fischer, T.C., Dupcak, R.J., Kroesen, P.L., Tung Pham, Olesin, A.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.01.1996
• Subjects: Adders; Circuits; Clocks; CMOS process; Delay; H infinity control; Logic design; Pipelines; Signal resolution; Wire
• ISBN: 9780780331365; 0780331362
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.1996.488716

A floating point unit initially implemented on a 300 MHz microprocessor in a 0.5 /spl mu/m/4-metal layer CMOS process and subsequently scaled for use in a 433 MHz version of the microprocessor in 0.35 /spl mu/m/4-metal layer CMOS process is described. This floating-point unit executes two floating-point instructions per cycle achieving 600 Mflops (peak) performance at 300 MHz and 366 Mflops (peak) at 433 MHz. It supports IEEE and VAX data types and rounding modes, including IEEE rounding to plus infinity and minus infinity. The floating-point unit contains 263,000 transistors and uses 6825 /spl mu/m/spl times/2025 /spl mu/m of chip area in the 0.35 /spl mu/m process. A single wire two phase system is used to provide a 3.3 ns cycle consisting of two 1.65 ns phases in the 300 MHz implementation, and a 2.3 ns cycle consisting of two 1.15 ns phases in the 433 MHz implementation.