An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor

• Published in: 2019 International Conference on Field-Programmable Technology (ICFPT) pp. 63 - 71
• Main Authors: Mashimo, Susumu, Inoue, Koji, Shioya, Ryota, Fujita, Akifumi, Matsuo, Reoma, Akaki, Seiya, Fukuda, Akifumi, Koizumi, Toru, Kadomoto, Junichiro, Irie, Hidetsugu, Goshima, Masahiro
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2019
• Subjects: field programmable gate array; multi port RAM; open source; out of order processor; RISC V; soft processor
• DOI: 10.1109/ICFPT47387.2019.00016

High-performance soft processors in field-programmable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack. An out-of-order (OoO) superscalar approach is a good candidate to improve performance in such cases, as evidenced from OoO hard processor studies. Recent studies have revealed, however, that conventional OoO processor components do not fit well in an FPGA, and it is thus important to carefully design such components for FPGA characteristics. Hence, we propose the RSD processor: a new, open-source OoO RISC-V soft processor optimized for an FPGA. The RSD supports many aggressive OoO execution features, like speculative scheduling, OoO memory instruction execution and disambiguation, a memory dependence predictor, and a non-blocking cache. While the RSD supports such aggressive features, it also leverages FPGA characteristics. Therefore, it consumes fewer FPGA resources than are consumed by existing OoO soft processors, which do not support such aggressive features well. We first introduce the end result of the RSD microarchitecture design and then describe several novel optimization techniques. The RSD achieves up to 2.5-times higher Dhrystone MIPS while using 60% fewer registers and 64% fewer lookup tables (LUTs) as compared to state-of-the-art, open-source OoO processors.