A 5.8-GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications

A 5.8-GHz fractional-N frequency synthesizer for IEEE 802.11a WLAN applications is designed in a 0.25μm CMOS process. The synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider and a digital third-order MASH delta-sigma modulator...

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Bibliographic Details
Published inASIC, 2003. Proceedings. 5th International Conference on Vol. 2; pp. 1074 - 1077 Vol.2
Main Authors Sau-Mou Wu, Ron-Yi Liu, Wei-Liang Chen
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Frequency conversion
Frequency modulation
Frequency synthesizers
Multi-stage noise shaping
Phase noise
Synthesizers
Voltage-controlled oscillators
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Summary:A 5.8-GHz fractional-N frequency synthesizer for IEEE 802.11a WLAN applications is designed in a 0.25μm CMOS process. The synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider and a digital third-order MASH delta-sigma modulator together. The VCO is capable of 240MHz tuning range and exhibits a phase noise of about -115dBc/Hz at 1MHz offset from the center frequency throughout the tuning range. The synthesizer has a bandwidth of 300KHz for a 35MHz reference and can achieve a close-in phase noise of about -80dBc/Hz while the total power consumption is 35mW from a single 2.5V supply.
ISBN:0780378946
078037889X
9780780378940
9780780378896
ISSN:1523-553X
DOI:10.1109/ICASIC.2003.1277398