Bunch of Wires Interface PHY Design for Multi-Chiplet Systems

With the increase in downscaling the improvement of system performance has been a tough task. To further improve the performance parameter of the system such as low power, high data rates technologies such as Multichip module (MCM), System in package (SiP) and the integration of chips on an active a...

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Bibliographic Details
Published in2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC) pp. 395 - 398
Main Authors Ahmed, Maudood, Chaudhary, Muhammad Waqas, Heinig, Andy
Format Conference Proceeding
LanguageEnglish
Published IEEE 07.12.2021
Subjects
Costs
Device-to-device communication
System performance
System-in-package
Topology
Transmitters
Wires
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DOI10.1109/EPTC53413.2021.9663983

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Summary:With the increase in downscaling the improvement of system performance has been a tough task. To further improve the performance parameter of the system such as low power, high data rates technologies such as Multichip module (MCM), System in package (SiP) and the integration of chips on an active and passive interposer is being used these days. The recently introduced Bunch of wires interface standard for chip to chip communication for short interface interconnects upto 11 mm length can serve the purpose. This paper presents Bunch of wires standard PHY design which consists of first ever implementation of transmitter (TX) and receiver (RX) architecture.
DOI:10.1109/EPTC53413.2021.9663983