NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad

Non-Volatile Memory technologies are rising as a candidate for a universal memory. NVMs offer solutions for the high power consumption that contemporary memory suffers from. Hence, we propose augmenting the traditional SRAM cache with an additional NVM device instead of entirely replacing SRAM with...

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Bibliographic Details
Published in2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) pp. 54 - 59
Main Authors Shalabi, Ameer, Paul, Kolin, Ghasempouri, Tara, Raik, Jaan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2020
Subjects
Computer architecture
Estimation
high performance
instruction cache
Integrated circuit modeling
low energy
Nonvolatile memory
NV SP
NVM
Performance evaluation
Phase change random access memory
scratchpad
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Summary:Non-Volatile Memory technologies are rising as a candidate for a universal memory. NVMs offer solutions for the high power consumption that contemporary memory suffers from. Hence, we propose augmenting the traditional SRAM cache with an additional NVM device instead of entirely replacing SRAM with NVM. The L1 instruction-cache is augmented with a Non-Volatile Scratch-Pad, coined NV-SP, that stores instructions causing the highest number of misses. Experiments were evaluated for performance and energy of the SRAM I-cache and the NV-SP when implemented using Magnetic RAM and Phase-Changing RAM technologies. Results have shown that MRAM NV-SP had effectively improved the performance of the I-cache.
ISSN:2159-3477
DOI:10.1109/ISVLSI49217.2020.00020