HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler

• Published in: International Conference on Field-programmable Logic and Applications pp. 380 - 381
• Main Authors: Kasgen, Philipp, Messelka, Mohamed, Weinhardt, Markus
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2021
• Subjects: C compiler; CGRA; Computational efficiency; Computer architecture; Energy efficiency; Field programmable gate arrays; FPU; Hardware; HPC; Multicore processing; Parallel processing; Reconfigurable Computing

The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained Field-Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The sa...