Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

• Published in: Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) pp. 57 - 59
• Main Authors: Lee, K.-W., Shin, H.J., Hwang, J.W., Nam, S.W., Moon, Y.J., Wee, Y.J., Kim, I.G., Park, W.J., Kim, J.H., Lee, S.J., Park, K.K., Kang, H.-K., Suh, K.-P.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004
• Subjects: Abrasives; Applied sciences; Atherosclerosis; Design. Technologies. Operation analysis. Testing; Dielectric devices; Dielectric materials; Electronics; Etching; Exact sciences and technology; Integrated circuits; Large scale integration; Lithography; Manufacturing processes; Microelectronic fabrication (materials and surfaces technology); Moon; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon carbide; Trench technology; Barrier layer; Polishing; Porous material; Damascene process; Microelectronic fabrication; Interconnection; Integrated circuit; Physical vapor deposition; Miniaturization; Multilevel system; Low k dielectric; Damaging; Via hole
• ISBN: 9780780383081; 0780383087
• DOI: 10.1109/IITC.2004.1345683

A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).