Fan-Out RDL-first Panel-Level Packaging for Heterogeneous Integration

In this study, the fan-out chip-last panel-level packaging for heterogeneous integrations is investigated. Emphasis is placed on the design, materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm x 10mm) and two small chips (7mm x 5mm) by a fan-out me...

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Bibliographic Details
Published in2020 IEEE 70th Electronic Components and Technology Conference (ECTC) pp. 339 - 347
Main Authors Lau, John H, Ko, Cheng-Ta, Yang, Kai-Ming, Peng, Chia-Yu, Xia, Tim, Lin, Puru Bruce, Chen, JJ, Huang, Po-Chun, Liu, Hsing Ning, Tseng, Tzvy-Jang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2020
Subjects
Bonding
Dielectrics
Electromagnetic compatibility
Metals
Packaging
Strips
Substrates
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Summary:In this study, the fan-out chip-last panel-level packaging for heterogeneous integrations is investigated. Emphasis is placed on the design, materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm x 10mm) and two small chips (7mm x 5mm) by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a 515mm x 510mm panel. Reliability assessments such as the thermal cycling of the heterogeneous integration of the 3-chip package printed circuit board (PCB) assembly are performed by a nonlinear temperature- and time-dependent finite element simulation.
ISSN:2377-5726
DOI:10.1109/ECTC32862.2020.00062