Scaling Constraints for Memristor-based Programmable Interconnect in Reconfigurable Computing Arrays

This paper presents and discusses several distinct, but interconnected, aspects of memristor-based switch and inter- connect implementation methodology. A detailed study has been conducted into the trade-offs between usability and performance with respect to several memristive designs, which directl...

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Bibliographic Details
Published in2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) pp. 102 - 107
Main Authors Murray, John J., Foshie, Adam Z., Ara Shawkat, Mst Shamim, Rose, Garrett S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2021
Subjects
FPGA
Interconnect
Memristor
Memristors
Neuromorphic
Performance evaluation
Programming
Random access memory
Routing
RRAM
Switches
Threshold voltage
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Summary:This paper presents and discusses several distinct, but interconnected, aspects of memristor-based switch and inter- connect implementation methodology. A detailed study has been conducted into the trade-offs between usability and performance with respect to several memristive designs, which directly relate to different properties of memristor devices. Performance comparisons are shown for a number of architectures, including an SRAM with a pass transistor, inline memristors, 1T1Rs, and 2T1Rs. Results are presented showing the impact of varying array sizes and implementations on the energy per pulse for a signal passing through such structures. While this work places more emphasis on fully connected routing for a cluster of neuromorphic cores, these aspects apply to many other cases and can be the source of tectonic hazards for non-paper designs.
ISSN:2159-3477
DOI:10.1109/ISVLSI51109.2021.00029