Theoretical Foundations of Memristor Cellular Nonlinear Networks: A DRM2-Based Method to Design Memcomputers With Dynamic Memristors

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 8; pp. 2753 - 2766
• Main Authors: Ascoli, Alon, Tetzlaff, Ronald, Kang, Sung-Mo, Chua, Leon O.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Capacitors; Cellular communication; cellular nonlinear networks; Computer architecture; Dynamical systems; Initial conditions; Mathematical model; memcomputing; Memristor; Memristors; Nonlinear dynamical systems; Nonlinear dynamics; Resistance; second-order dynamic route map; second-order state dynamic route; state dynamic portrait; Switches; Switching; System effectiveness; Systems theory
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.2978460

In the memristive version of a standard space-invariant Cellular Nonlinear Network, each cell accommodates one first-order non-volatile memristor in parallel with a capacitor. In case, the resistance switching memory may only undergo almost-instantaneous switching transitions between two possible resistive states, acting at any time, as either the on or the off resistor, the processing elements effectively operate as first-order dynamical systems, and the classical Dynamic Route Map technique may be applied to investigate their operating principles. On the contrary, in case the memristors experience smooth conductance changes, as the bioinspired array implements memcomputing paradigms, each cell truly behaves as a second-order dynamical system. The recent extension of the Dynamic Route Map analysis tool to systems with two degrees of freedom constitutes a powerful technique to investigate the nonlinear dynamics of memristive cellular networks in these scenarios. This paper exploits this system-theoretic technique, called Second-Order Dynamic Route Map, to introduce a novel systematic procedure to design memristive arrays, in which a given memcomputing task is executed by ensuring that, depending upon the network inputs and initial conditions, the analogue dynamic routes of the states of the processing elements, namely capacitor voltages and memristor states, asymptotically converge toward pre-defined stable equilibria.