Testing of Configurable 8T SRAMs for In-Memory Computing

In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Various IMC memories using 8T static random access memory (SRAM) cell have been reported. Some of them, the memory array can provide SRAM and ternary con...

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Bibliographic Details
Published in2020 IEEE 29th Asian Test Symposium (ATS) pp. 1 - 5
Main Authors Li, Jin-Fu, Tsai, Tsai-Ling, Hsu, Chun-Lung, Sun, Chi-Tien
Format Conference Proceeding
LanguageEnglish
Published IEEE 23.11.2020
Subjects
Circuit faults
Computer architecture
content addressable memory
Decoding
In-memory computing
March-like test
Microprocessors
Random access memory
Registers
static random access memory
Testing
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Summary:In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Various IMC memories using 8T static random access memory (SRAM) cell have been reported. Some of them, the memory array can provide SRAM and ternary content addressable memory (TCAM) function. In this paper, a March-like test algorithm is proposed, which requires 10 × 2 p Read/Write operations, (2 q + 4m) Compare operation, and (2 r+1 + 4m) Erase operations to cover simple SRAM faults and TCAM Comparison faults, for an IMC 8T SRAM providing 2 p ×w-bit SRAM and m× 2 q−1 -bit TCAM, where p = q+r and m = 2 r ×w.
ISSN:2377-5386
DOI:10.1109/ATS49688.2020.9301535