An Open-source Framework for Autonomous SoC Design with Analog Block Generation

• Published in: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC) pp. 141 - 146
• Main Authors: Ajayi, Tutu, Kamineni, Sumanth, Cherivirala, Yaswanth K, Fayazi, Morteza, Kwon, Kyumin, Saligane, Mehdi, Gupta, Shourya, Chen, Chien-Hen, Sylvester, Dennis, Blaauw, David, Dreslinski, Ronald, Calhoun, Benton, Wentzloff, David D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.10.2020
• Subjects: analog generator; analog synthesis; Generators; Phase locked loops; Prototypes; Random access memory; SoC generator; Temperature sensors; Very large scale integration
• ISSN: 2324-8440
• DOI: 10.1109/VLSI-SOC46417.2020.9344104

We present the world's first autonomous mixed-signal SoC framework, driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process-agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog blocks using a cell-based design methodology. Our approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different processes and requires no-human-in-the-Ioop, dramatically accelerating design time.