RED-SEA: Network Solution for Exascale Architectures

• Published in: 2022 25th Euromicro Conference on Digital System Design (DSD) pp. 712 - 719
• Main Authors: Biagioni, Andrea, Cretaro, Paolo, Frezza, Ottorino, Cicero, Francesca Lo, Lonardo, Alessandro, Martinelli, Michele, Paolucci, Pier Stanislao, Pastorelli, Elena, Simula, Francesco, Turisini, Matteo, Vicini, Piero, Ammendola, Roberto, Bernier-Bruna, Pascale, Chen, Claire, Derradji, Said, Guez, Stephane, Lagadec, Pierre-Axel, Pichon, Gregoire, Walter, Etienne, De Gassowski, Gaetan, Hautreaux, Matthieu, Mathieu, Stephane, Moreau, Gilles, Perache, Marc, Taboada, Hugo, Hoefler, Torsten, Schneider, Timo, Barnaba, Matteo, Brandino, Giuseppe Piero, De Giorgi, Francesco, Poggi, Matteo, Mavroidis, Iakovos, Papaefstathiou, Yannis, Tampouratzis, Nikolaos, Kalisch, Benjamin, Krackhardt, Ulrich, Nuessle, Mondrian, Xirouchakis, Pantelis, Mageiropoulos, Vangelis, Gianioudis, Michalis, Loukas, Harisis, Ioannou, Aggelos, Kallimanis, Nikos, Chrysos, Nikos, Katevenis, Manolis, Frings, Wolfang, Gottwald, Dominik, Guimaraes, Felime, Holicki, Max, Marx, Volker, Muller, Yannik, Clauss, Carsten, Falter, Hugo, Huang, Xu, Barillao, Jennifer Lopez, Moschny, Thomas, Pickartz, Simon, Alfaro, Francisco J., Escudero-Sahuquillo, Jesus, Garcia, Pedro Javier, Quiles, Francisco J., Sanchez, Jose L., Castello, Adrian, Duro, Jose, Gomez, Maria Engracia, Quintana, Enrique, Sahuquillo, Julio, Stabile, Eugenio
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2022
• Subjects: Adaptation models; Analytical models; Artificial intelligence; collective communication; congestion mechanism; datacenter; Hardware; HPC; Interconnect; Low-Latency Ethernet; QoS; Routing; Security; Software
• ISSN: 2771-2508
• DOI: 10.1109/DSD57027.2022.00100

In order to enable Exascale computing, next generation interconnection networks must scale to hundreds of thousands of nodes, and must provide features to also allow the HPC, HPDA, and AI applications to reach Exascale, while benefiting from new hardware and software trends. RED-SEA will pave the way to the next generation of European Exascale interconnects, including the next generation of BXI, as follows: (i) specify the new architecture using hardware-software co-design and a set of applications representative of the new terrain of converging HPC, HPDA, and AI; (ii) test, evaluate, and/or implement the new architectural features at multiple levels, according to the nature of each of them, ranging from mathematical analysis and modeling, to simulation, or to emulation or implementation on FPGA testbeds; (iii) enable seamless communication within and between resource clusters, and therefore development of a high-performance low latency gateway, bridging seamlessly with Ethernet; (iv) add efficient network resource management, thus improving congestion resiliency, virtualization, adaptive routing, collective operations; (v) open the interconnect to new kinds of applications and hardware, with enhancements for end-to-end network services - from programming models to reliability, security, low- latency, and new processors; (vi) leverage open standards and compatible APIs to develop innovative reusable libraries and Fabrics management solutions.