Demonstration of Fan-out Silicon Photonics Module for Next Generation Co-Packaged Optics (CPO) Application

This paper presents the design and demonstration of a co-packaged optical engine using Rockley's co-designed chipsets, where the fan-out Electrical IC (EIC) substrate is flip-chip bonded to the Photonics Integrated Circuit (PIC), then socketed to the switch ASIC board. Combining fan-out, flip-c...

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Bibliographic Details
Published in2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) pp. 394 - 402
Main Authors Chou, Bruce, Sawyer, Brett M., Lyu, Gap, Timurdugan, Erman, Minkenberg, Cyriel, Zilkie, Aaron J., McCann, David
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2022
Subjects
Adaptive optics
Co-packaged optics
Costs
elastomer socket
Flip-chip devices
Integrated optics
Optical switches
Packaging
Signal integrity
silicon photonics
wafer-level fan-out
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Summary:This paper presents the design and demonstration of a co-packaged optical engine using Rockley's co-designed chipsets, where the fan-out Electrical IC (EIC) substrate is flip-chip bonded to the Photonics Integrated Circuit (PIC), then socketed to the switch ASIC board. Combining fan-out, flip-chip, and socketing optimizes signal integrity and material/packaging cost for the PIC and EIC, while maximizing integration density and rework-ability of the optical engines. The proof-of-concept is realized using our 25 Gbps/ch chipset, and the testing results proved that, not only does our packaging method enable fully functional testing, its impact to the bandwidth of the chipset is negligible. Therefore, the optical engine packaging can be applied to next generation chipset without losing signal integrity and power.
ISSN:2377-5726
DOI:10.1109/ECTC51906.2022.00071