Bit-Serial multiplier based Neural Processing Element with Approximate adder tree

Deep learning algorithms are computationally intensive and require dedicated hardware accelerators. Deep learning algorithms repeat multiply-accumulate (MAC) operations. This process produces a large number of partial sums that account for about 60% of the total logic. Therefore, optimizing multi-op...

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Bibliographic Details
Published in2020 International SoC Design Conference (ISOCC) pp. 286 - 287
Main Authors Jo, Cheolwon, Lee, KwangYeob
Format Conference Proceeding
LanguageEnglish
Published IEEE 21.10.2020
Subjects
Accelerator
Adders
Approximation algorithms
Deep learning
LOA
Logic gates
low power
MOA
Mobile handsets
Performance evaluation
Resource management
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Summary:Deep learning algorithms are computationally intensive and require dedicated hardware accelerators. Deep learning algorithms repeat multiply-accumulate (MAC) operations. This process produces a large number of partial sums that account for about 60% of the total logic. Therefore, optimizing multi-operand adders (MOA) that add these partial sums can reduce the high resource utilization of deep learning accelerators. This study designed a neural processing element with approximate adders that reduces resource utilization without changing the accuracy of deep learning algorithms by using the fault tolerance property of deep learning algorithms. As a result, the accuracy dropped by only 0.04 % with 4.7% less resource usage.
DOI:10.1109/ISOCC50952.2020.9332993