PipeRench: A virtualized programmable datapath in 0.18 micron technology

• Published in: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) pp. 63 - 66
• Main Authors: Schmit, H., Whelihan, D., Tsai, A., Moe, M., Levine, B., Reed Taylor, R.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Acceleration; Application software; Applied sciences; Circuit properties; Costs; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Fabrics; Feedback; Finite impulse response filter; Frequency filters; Hardware; Integrated circuit interconnections; Integrated circuits; Integrated circuits by function (including memories and processors); Pipeline processing; Runtime; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Performance evaluation; Computer hardware; Integrated circuit; Finite impulse response filter; Transistor; Reconfigurable architectures; Microprocessor; Digital signal processor; Implementation
• ISBN: 9780780372504; 0780372506
• DOI: 10.1109/CICC.2002.1012767

PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managed dynamic reconfiguration. This capability provides application portability and scalability without redesign or recompilation. This paper describes the implementation of PipeRench in a 0.18 micron process. The implementation has 3.65 million transistors and runs at 120 MHz. Performance is competitive with high-end commercial DSP architectures and more than five times faster than a commercial microprocessor. Executing at 33 MHz, an FIR filter without virtualization consumes 519 mW. When virtualization is required, the implementation consumes approximately 675 mW.