Study of Submicron Panel-Level Packaging in Mass-Production

• Published in: 2021 IEEE 71st Electronic Components and Technology Conference (ECTC) pp. 2105 - 2110
• Main Authors: Shinoda, Ken-ichiro, Shelton, Douglas, Suda, Hiromi, Goto, Yoshio, Urushihara, Kosuke, Mori, Ken-Ichiro
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2021
• Subjects: Advanced Packaging; Fan-Out; Image resolution; Lithography; Manufacturing; Optics; Packaging; Panel Exposure System; Panel-Level Packaging; Printed circuits; Stepper; Submicron; Wafer scale integration
• ISSN: 2377-5726
• DOI: 10.1109/ECTC32696.2021.00331

Heterogeneous Integration is evolving to acquire finer resolution and larger devices to leverage the advantages provided by More-than-Moore manufacturing and packaging technologies that can help maximize the efficiency and increase the bandwidth of high performance computing systems. Advanced Packaging with submicron Redistribution Layers (RDL) and large package sizes is one of solutions that can help enable complex Heterogeneous Integration designs for applications including Artificial Intelligence (AI), 5G communication and autonomous driving. For systems requiring large package sizes, Panel Level Packaging (PLP) can offer efficiency and cost advantages over Wafer Level Packaging (WLP). PLP however poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first patterning exposure tool or stepper that is capable of submicron resolution on 500 mm panels. This new panel exposure tool is equipped with wide-field projection optics that offer a large \mathrm{52}\ \text{mm}\times \mathrm{68}\ \text{mm} image field and 0.24 NA that is optimum for submicron resolution. The stepper also features a newly developed panel handling system for processing up to \mathrm{515}\times \mathrm{515}\ \text{mm} panels. In this paper, we will report on evaluation results of fine patterning for a mass-production panel level packaging process using the new submicron resolution panel stepper. We will also discuss current fine-PLP status, challenges and solutions. One topic of our study is patterning uniformity. In 2020, we reported patterning uniformity improvement technology using a glass substrate. This study attempts to apply the technology described in 2020 to improve pattern uniformity on Copper Clad Laminate (CCL) substrates that are widely used in printed circuit board (PCB) manufacturing. In addition, we will report on results of studies of stitching capability and alignment accuracy on substrates with die placement error. Our study also explored warped panel handling including the development of a multi-vacuum line chucking system.