Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection

• Published in: 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP) pp. 213 - 216
• Main Authors: Loh, Johnson, Wen, Jianan, Gemmeke, Tobias
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2020
• Subjects: 1D convolutional neural networks (CNN); application specific integrated circuit (ASIC); Clocks; Computer architecture; digital signal processing (DSP); discrete wavelet transform (DWT); Discrete wavelet transforms; electrocardiogram (ECG) classification; Electrocardiography; Hardware; Logic gates; low energy per solution; Quantization (signal)
• ISSN: 2160-052X
• DOI: 10.1109/ASAP49362.2020.00042

This work implements a digital signal processing (DSP) accelerator for ECG signal classification. Targeting the integration into wearable devices for 24/7 monitoring, low energy consumption per classification is a key requirement, while maintaining a high classification accuracy at the same time. Co-optimization on algorithm and hardware level led to an architecture consisting mostly of convolution operations in the processing pipeline. The realized discrete wavelet transform and convolutional neural network (CNN) is utilized for continuous time-sequence classification in a sliding-window approach moving away from sample/batch-based processing typical for CNNs. In contrast to previous hardware realizations in this domain, the proposed design was validated using the benchmark dataset from the demanding CinC challenge 2017. The architecture achieves a competitive 0.781 Fl-score with only 5597 trainable parameters reducing the computational complexity of state-of-the-art ECGDNN software solutions by three orders of magnitude. Synthesis in a 22-nm FDSOI-CMOS technology features 0.783 \muJ per solution meeting requirements for edge device operation at high-end classification performance.