Effective and efficient test architecture design for SOCs

• Published in: Proceedings - International Test Conference pp. 529 - 538
• Main Authors: Goel, S.K., Marinissen, E.J.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Algorithm design and analysis; Applied sciences; Benchmark testing; Circuit testing; Computer architecture; Design. Technologies. Operation analysis. Testing; Digital integrated circuits; Electronics; Exact sciences and technology; Heuristic algorithms; Integrated circuit testing; Integrated circuits; Laboratories; Logic testing; Scheduling algorithm; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing, measurement, noise and reliability; Lower bound; Series parallel connection; Modular architecture; Integrated circuit testing; Integrated circuit; Heuristic method; Design for testability; System on a chip; Bus(channel); Algorithm
• ISBN: 9780780375420; 0780375424
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.2002.1041803

This paper deals with the design of test architectures for modular SOC testing. These architectures consist of wrappers and TAMs (test access mechanisms). For a given SOC, with specified parameters of modules and their tests, we design architectures which minimize the required ATE vector memory depth and test application time. In this paper, we formulate the problems of test architecture design both for modules with fixed- and flexible-length scan chains. Subsequently, we derive a formulation of an architecture-independent test time lower bound for SOCs and list the lower bound values for the 'ITC'02 SOC test benchmarks'. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and testrail architectures with serial and parallel test schedules. Experimental results for the 'ITC'02 SOC test benchmarks' show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.