Formal verification of data-path circuits based on symbolic simulation

This paper presents a formal verification method based on logic simulation. In our method, using symbolic values even circuits which include data paths can be verified without abstraction of data paths. Our verifier extracts a transition relation from the state graph (given as a specification) which...

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Bibliographic Details
Published inProceedings - Asian Test Symposium pp. 329 - 336
Main Authors Morihiro, Y., Toneda, T.
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 2000
Subjects
Circuit simulation
Computational modeling
Computer science
Computer simulation
Data mining
Formal verification
Information science
Logic circuits
Logic design
Workstations
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Summary:This paper presents a formal verification method based on logic simulation. In our method, using symbolic values even circuits which include data paths can be verified without abstraction of data paths. Our verifier extracts a transition relation from the state graph (given as a specification) which is expressed using symbolic values, and verifies based on simulation using those symbolic values if the circuit behaves correctly with respect to each transition of the specification. If the verifier terminates with "correct", then we can guarantee that for any applicable input vector sequences, the circuit and the specification behaves identically. We implemented the proposed method on a Unix workstation and verified some FIFO and LIFO circuits by using it.
Bibliography:SourceType-Scholarly Journals-2
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ObjectType-Conference Paper-1
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ISBN:0769508871
9780769508870
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2000.893645