Delivering error detection capabilities into a field programmable device: the HORUS processor case study

• Published in: 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings pp. 418 - 421
• Main Authors: Rodriguez, F., Campelo, J.C., Serrano, J.J.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY IEEE 2002
• Subjects: Applied sciences; Computer aided software engineering; Computer vision; Design methodology; Design. Technologies. Operation analysis. Testing; Electronics; Error correction; Exact sciences and technology; Fault detection; Fault tolerance; Integrated circuits; Integrated circuits by function (including memories and processors); Modems; Reduced instruction set computing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Testing; Case study; Performance evaluation; RISC processor; Integrated circuit; Reuse; Error detection; System on a chip; Flexibility; Implementation
• ISBN: 0780375742; 9780780375741
• DOI: 10.1109/FPT.2002.1188724

Designing a complete SoC or reuse SoC components to create a complete system is a common task nowadays. The flexibility offered by current design flows offers the designer an unprecedented capability to incorporate more and more demanded features like error detection and correction mechanisms to increase the system dependability. This is especially true for programmable devices, were rapid design and implementation methodologies are coupled with testing environments that are easily generated and used. This paper describes the design of the HORUS processor, a RISC processor augmented with a concurrent error mechanism, the architectural modifications needed on the original design to minimize the resulting performance penalty.