Cyclic greedy generation method for limited number of IDDQ tests

This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it gr...

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Bibliographic Details
Published inProceedings - Asian Test Symposium pp. 362 - 366
Main Authors Shinogi, T., Ushio, M., Hayashi, T.
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 2000
Subjects
Circuit faults
Circuit testing
CMOS logic circuits
Electrical fault detection
Electronic equipment testing
Fault detection
Logic testing
Random number generation
Sequential analysis
Test pattern generators
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Summary:This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85&89 circuits.
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ISBN:0769508871
9780769508870
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2000.893650