Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging

Voltage surges induced by electrostatic discharge (ESD) impacts on the backside of an integrated circuit (IC) chip in flip-chip packaging potentially causes reliability problems and even leads to malfunctioning. On-chip voltage waveform monitor circuits on its frontside evaluate the surge as high as...

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Bibliographic Details
Published in2022 IEEE International Reliability Physics Symposium (IRPS) pp. P14-1 - P14-6
Main Authors Wadatsumi, Takuya, Kawai, Kohei, Hasegawa, Rikuu, Miki, Takuji, Nagata, Makoto, Muramatsu, Kikuo, Hasegawa, Hiromu, Sawada, Takuya, Fukushima, Takahito, Kondo, Hisashi
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2022
Subjects
Electrostatic discharge
Electrostatic discharges
Flip-chip devices
Full-wave simulation
On-chip monitor
Packaging
Semiconductor device measurement
Silicon
Surges
Voltage measurement
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Summary:Voltage surges induced by electrostatic discharge (ESD) impacts on the backside of an integrated circuit (IC) chip in flip-chip packaging potentially causes reliability problems and even leads to malfunctioning. On-chip voltage waveform monitor circuits on its frontside evaluate the surge as high as 200 mV when ESD gun at 200 V is discharged to the Si substrate backside through the contact resistance of 5 kto the backside of a 350 µm thick Si substrate. The distribution of voltages over the frontside area of an IC chip is measured and explained with full-system level backside ESD simulation.
ISSN:1938-1891
DOI:10.1109/IRPS48227.2022.9764457