Ternary Sense Amplifier Design for Ternary SRAM

This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-to-back structure, and is configured as a latch type. The trade-off relationship between sensing...

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Bibliographic Details
Published in2021 18th International SoC Design Conference (ISOCC) pp. 151 - 152
Main Authors Choi, Minjeong, Choi, Youngchang, Kim, Sunmean, Kang, Seokhyeong
Format Conference Proceeding
LanguageEnglish
Published IEEE 06.10.2021
Subjects
Fabrication
Inverters
Latches
Multi-Valued Logic
Multivalued logic
Random access memory
Semiconductor device modeling
Sense Amplifier
Sensors
Ternary SRAM
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Summary:This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-to-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size. The T-SA may enable the realization of a memory array with ternary logic in a Multi-Valued Logic system.
DOI:10.1109/ISOCC53507.2021.9613911