Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors

• Published in: 2021 IEEE International Electron Devices Meeting (IEDM) pp. 37.2.1 - 37.2.4
• Main Authors: Lin, Y., Shen, P.-C., Su, C., Chou, A.-S., Wu, T., Cheng, C.-C., Park, J.-H., Chiu, M.-H., Lu, A.-Y., Tang, H.-L., Tavakoli, M. M., Pitner, G., Ji, X., McGahan, C., Wang, X., Cai, Z., Mao, N., Wang, J., Wang, Y., Tisdale, W., Ling, X., Aidala, K. E., Tung, V., Li, J., Zettl, A., Wu, C.-I., Guo, Jing, Wang, H., Bokor, J., Palacios, T., Li, L.-J., Kong, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 11.12.2021
• Subjects: Contact resistance; Electron devices; Ohmic contacts; Passivation; Performance evaluation; Transistors; Two dimensional displays
• ISSN: 2156-017X
• DOI: 10.1109/IEDM19574.2021.9720668

Two-dimensional (2D) semiconductors are expected to have exceptional properties for ultimately scaled transistors, but forming ohmic contact to them has been challenging, which tremendously limit the transistor performance. In this paper, we review the recent research progress on the elimination of different gap-state pinning effects, including defect-induced gap states (DIGS) and metal-induced gap states (MIGS). Specifically, an oxygen passivation method and a semimetallic contact technology were developed to reduce the DIGS and MIGS, respectively. Based on these approaches, much improved contact resistance and on-state current were observed. Key device metrics were extracted on these high-performance transistors, which reveals future directions for further improving the device performance.