Controller module implementation to reduce interrupt in CNPC uplink

The unmanned aerial vehicle is used in diverse area. In order to make more use of the unmanned aerial vehicle, reliable communication system is required. CNPC has been developed to standardize the communication system for unmanned aerial vehicle over 150kg. CNPC uplink should support diverse UAV in...

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Bibliographic Details
Published in2021 International Conference on Artificial Intelligence in Information and Communication (ICAIIC) pp. 295 - 297
Main Authors Mun, GwonHan, Hong, Tae Chul, Kim, DeaHo
Format Conference Proceeding
LanguageEnglish
Published IEEE 13.04.2021
Subjects
Artificial intelligence
CNPC
Communication systems
FPGA
MOPS
Operating systems
Reliability
Timing
Timing diagram
UAV
Unmanned aerial vehicles
Uplink
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Summary:The unmanned aerial vehicle is used in diverse area. In order to make more use of the unmanned aerial vehicle, reliable communication system is required. CNPC has been developed to standardize the communication system for unmanned aerial vehicle over 150kg. CNPC uplink should support diverse UAV in TDD. To implement CNPC in real world, operating system and FPGA should be used with the interface between the two. To reduce the use of interrupts in uplink implementations on FPGA, simple controller is designed to generate signals which act as the interrupts whenever other user message is needed. To implement this controller in FPGA, this paper deals with timing diagram for this module.
DOI:10.1109/ICAIIC51459.2021.9415209