High Volume Semiconductor Manufacturing Using Nanoimprint Lithography
Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In this work, we review progress on pattern capability, throughput, mask life and overlay.
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Published in | 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) pp. 1 - 4 |
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Main Authors | , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.04.2020
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Abstract | Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In this work, we review progress on pattern capability, throughput, mask life and overlay. |
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AbstractList | Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In this work, we review progress on pattern capability, throughput, mask life and overlay. |
Author | Cherala, Anshuman Hayashi, Tatsuya Komaki, Takamitsu Morimoto, Osamu Choi, Jin Morohoshi, Hiroshi Takabayashi, Yukio Zhang, Wei Im, Se-Hyuk Meissl, Mario Hiura, Mitsuru Iwanaga, Takehiko Sakai, Keita |
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SubjectTerms | Actuators Bending Costs Distortion HODC Manufacturing mask life nanoimprint lithography NIL overlay Random access memory resolution Throughput |
Title | High Volume Semiconductor Manufacturing Using Nanoimprint Lithography |
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