Core-based scan architecture for silicon debug

In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained...

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Bibliographic Details
Published inProceedings - International Test Conference pp. 638 - 647
Main Authors Vermeulen, B., Waayers, T., Goel, S.K.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 2002
Subjects
Applied sciences
Chip scale packaging
Circuit testing
Computational efficiency
Design methodology
Electronics
Exact sciences and technology
Integrated circuit modeling
Laboratories
Manufacturing
Silicon
System testing
Testing, measurement, noise and reliability
Time to market
Test
Gain
Implementation
Debugging
Large scale system
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Summary:In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained using the experiences gained from two large Philips system chips that each utilize core-based design and test, and scan-based silicon debug. The results of an area-cost evaluation of the presented architecture for these two large system chips are also presented.
ISBN:9780780375420
0780375424
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2002.1041815