Optimizing parallel bitonic sort

• Published in: Proceedings - International Parallel Processing Symposium pp. 303 - 309
• Main Authors: Ionescu, M.F., Schauser, K.E.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 1997
• Subjects: Algorithm design and analysis; Application software; Computer networks; Computer science; Concurrent computing; Modems; Parallel algorithms; Parallel machines; Phase change random access memory; Sorting
• ISBN: 0818677937; 9780818677939
• ISSN: 1063-7133
• DOI: 10.1109/IPPS.1997.580914

Sorting is an important component of many applications, and parallel sorting algorithms have been studied extensively in the last three decades. One of the earliest parallel sorting algorithms is bitonic sort, which is represented by a sorting network consisting of multiple butterfly stages. The paper studies bitonic sort on modern parallel machines which are relatively coarse grained and consist of only a modest number of nodes, thus requiring the mapping of many data elements to each processor. Under such a setting optimizing the bitonic sort algorithm becomes a question of mapping the data elements to processing nodes (data layout) such that communication is minimized. The authors developed a bitonic sort algorithm which minimizes the number of communication steps and optimizes the local computation. The resulting algorithm is faster than previous implementations, as experimental results collected on a 64 node Meiko CS-2 show.