Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors

We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its per...

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Bibliographic Details
Published inProceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) pp. 226 - 231
Main Authors Velev, M.N., Bryant, R.E.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Automatic test pattern generation
Boolean functions
Circuits
Computer science
Data structures
Formal verification
Microprocessors
Permission
Probes
VLIW
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Summary:We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas. We reassess optimizations previously used to speed up the formal verification and probe future challenges.
ISBN:1581132972
9781581132977
ISSN:0738-100X